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sy89113u 2.5v low jitter, low skew 1:12 lvds fanout buffer with 2:1 input mux and internal termination precision edge is a registered trademark of micrel, inc. mlf and micro leadframe are trademarks of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com march 2005 m9999-03290 5 hbwhelp@micrel.com or (408) 955-1690 general description the sy89113u is a 2.5v low jitter, low skew, 1:12 lvds fanout buffer optimized for precision telecom and enterprise server dist ribution applications. the input includes a 2:1 mux for clock switchover applications. unlike other multiplexers, this input includes a unique isolation design that minimizes channel-to-channel crosstalk. the sy89113u distributes clock frequencies from dc to >1ghz guaranteed over temperat ure and voltage. the sy89113u incorporates a sy nchronous output enable (en) so that the outputs will only be enabled/disabled when they are already in the low state. clk0 differential input includes micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (ac- or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor netwo rks in the signal path. clk1 differential input includes a new version of micrel's unique, any-input ar chitecture that directly interfaces with single-ended ttl/cmos logic (including 3.3v logi c), single-ended lvpecl, differential (ac- or dc-coupled) lvds, hstl, cml, and lvpecl logic levels as small as 200mv (400mv pp ). clk1 input requires external termination. lvds output swing 325mv into 100 ? with extremely fast rise/fall time guaranteed to be less than 250ps. the sy89113u operates from a 2.5v5% supply and is guaranteed over the full industrial temperature range of -40c to +85c. the sy89113u is part of micrel's high-speed, precision edge ? product line. all support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? selects between 1 of 2 inputs, and provides 12 precision, low skew lvds output copies ? guaranteed ac performance over temperature and voltage: ? dc to >1ghz throughput ? <975ps propagation delay clk0-to-q ? <250ps rise/fall time ? <25ps output-to-output skew ? ultra-low jitter design: ? <1ps rms random jitter ? <10ps pp total jitter (clock) ? <1ps rms cycle-to-cycle jitter ? <0.7ps rms crosstalk induced jitter ? unique, patent-pending 2:1 input mux provides superior isolation to minimize channel-to-channel crosstalk ? clk0 input features a unique, patent-pending input termination and vt pin that accepts ac- and dc- coupled inputs (cml, lvpecl, lvds) ? clk1 accepts virtually any logic standard: ? single-ended: ttl/cmos (including 3.3v logic), lvpecl ? differential: lvpecl, lvds, cml, hstl ? 325mv lvds-compatible output swing ? power supply: 2.5v + 5% ? industrial temperature range ?40c to +85c ? available in 44-pin (7mm x 7mm) mlf? package applications ? multi-processor server ? sonet/sdh clock/data distribution ? fibre channel distribution ? gigabit ethernet clock distribution
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 2 functional block diagram
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 3 ordering information (1) part number package type operating range package marking lead finish sy89113umg mlf-44 industrial sy89113u with pb-free bar-line indicator nipdau pb-free sy89113umgtr (2) mlf-44 industrial sy89113u with pb-free bar-line indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44-pin mlf tm (mlf-44) truth table en clk_sel q /q h l clk0 /clk0 h h clk1 /clk1 l x l (1) h (1) note: 1. transition occurs on next negative transition of the non-inverted input.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 4 pin description pin number pin name pin function 1, 6, 11, 22, 34 gnd, exposed pad ground. gnd pins and exposed pad must both be connected to the most negative potential of chip the ground. 2, 5 clk0, /clk0 differential inputs: this input pair is a diffe rential signal input to the device. input accepts ac- or dc-coupled signals as small as 100mv (200mv pp ). each pin of the pair internally terminates to a vt pin through 50 ? . note that this input defaults to an indeterminate state if left open. pleas e refer to the "clk0 input interface applications" section for more details. 3 vt0 input termination center-tap: each side of the differential input pair clk0, /clk0 terminates to the vt pin. the vt pin pr ovides a center-tap to a termination network for maximum interface flexibility. see ?c lk0 input interface applications? section for more details. for dc-coupled cml or lvds inputs, the vt pin is left floating. 4 vref-ac0 reference voltage: this output biases to v cc ?1.2v. it is used when ac-coupling the input clk0. for ac-coupled applications, connect vref-ac0 to the vt0 pin and bypass with 0.01f low esr capacitor to v cc . see ?clk0 input interface applications? section for more details. maximum sink/source current is 1.5ma. due to the limited drive capability, the vref-ac0 pin is only intended to drive its respective input pin. 7 se-term input termination pin: when clk1 is driv en by a single-ended ttl/cmos signal, tie this pin to gnd. in all other modes, let this pin float. see ?clk1 interface applications? section for more details. 8, 10 clk1, /clk1 differential inputs: this input pair is a diffe rential signal input to the device. this input accepts any-logic standard as small as 200mv (400mv pp ). note that this input defaults to an indeterminate state if left open . tie either the true or the complement input to ground while the other input is f loating. this input can be used for single- ended signals (including ttl/cmos signals fr om a 3.3v driver). see ?clk1 input interface applications? section for more details. 9 vbb1 reference voltage: this output biases to v cc ?1.425v. vbb1 is designed to act as a switching reference for the clk1 and /clk1 inputs when configured in single-ended pecl input mode. vbb1 can be used for ac-coupling of clk1, see figure 4d for details. maximum sink/source current is 1.5ma. due to the limited drive capability, the vbb1 pin is only intended to dr ive its respective input pin. 12 en this single-ended, ttl/cmos-compatible in put functions as a synchronous output enable. the synchronous enable ensures that enable/disable will only occur when the outputs are in a logic low state. note t hat this input is internally connected to a 25k ? pull-up resistor and will default to lo gic high state (enable) if left open. 13, 23, 28, 33, 43 vcc positive power supply. bypass with 0.1f//0.01f low esr capacitors and place as close to the vcc pins as possible. 44 clk_sel this single-ended, ttl/cmos-compatible inpu t selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if open. 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 q10, /q10 q11, /q11 differential lvds outputs: these lvds output pairs are the precision, low skew copies of the selected input. please refer to the, ?truth table? below for details. unused output pairs should be terminated with 100 ? across the pair. each output is designed to drive 325mv into 100 ? . see the ?lvds output interface applications? section for more details.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 5 absolute maximum ratings (1) supply voltage (v cc ) .......................... ?0.5v to +4.0v input voltage (differential input clk0, clk1 (4, 5) ).. ?0.5v to v cc current on reference voltage outputs source or sink current on vref-ac0, vbb1.....2ma termination current source or sink current on vt0 ................100ma input current source or sink current on clk0, /clk0 ...50ma lead temperature (solderi ng, 20 sec.) .......... +260c storage temperature (t s ) ................. ?65c to 150c operating ratings (2) supply voltage (v cc ).................. +2.375v to +2.625v ambient temperature (t a )................ ?40c to +85c package thermal resistance (3) mlf? ( ja ) still-air ................................................ 24c/w mlf? ( jb ) junction-to-board ................................. 8c/w dc electrical characteristics (6) t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 2.625 v i cc power supply current no load, max. v cc 240 330 ma r in input resistance (clk0-to-v t ) 45 50 55 ? r diff_in differential input resistance (clk0-to-/clk0) 90 100 110 ? input high voltage (clk0, /clk0) 1.2 v cc v (clk1, /clk1) note 4 0.2 v cc v v ih note 5 1.2 3.6 input low voltage (clk0, /clk0) 0.1 v cc v (clk1, /clk1) note 4 0.2 v v il note 5 0 v input voltage swing (clk0, /clk0) see figure 1a. 0.1 v cc v v in (clk1, /clk1) see figure 1a. 0.2 v differential input voltage swing |clk0-to-/clk0| see figure 1b. 0.2 v v diff_in |clk1-to-/clk1| see figure 1b. 0.4 v v t0 clk0-to-v t0 (clk0, /clk0) 1.28 v v ref-ac0 output reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v v bb1 output reference voltage v cc ?1.525 v cc ?1.425 v cc ?1.325 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ra tings conditions for extended periods ma y affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the devices most negative potential on the pcb . ja and jb values are determined for a 4-layer board in still-air, unless otherwise stated. 4. se-term not connected. 5. using single-ended ttl/cmos input signals, se-term connects to gnd. see figure 4f. 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 6 lvds outputs dc electrical characteristics (7) v cc = +2.5v 5%; t a = ?40c to +85c; r l = 100 ? across the output pair, unless otherwise stated. symbol parameter condition min typ max units v out output voltage swing q, /q see figure 1a. 250 325 mv v diff-out differential output voltage swing q, /q see figure 1b. 500 650 mv v ocm output common mode voltage 1.125 1.275 v ? v os change in v os between complementary output states 25 mv lvttl/cmos dc electri cal characteristics (7) v cc = +2.5v 5%; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current ?125 30 a i il input low current ?300 a note: 7. the circuit is designed to meet the dc specifications, shown in the above table, after thermal equilibrium has been establis hed.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 7 ac electrical characteristics (8) v cc = +2.5v 5%; t a = ?40c to + 85c, r l = 100 ? across the output pair, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency v out 200mv 1 ghz v in 100mv 625 750 975 ps v in 200mv 700 900 1200 ps t pd propagation delay clk0-to-q clk1-to-q clk_sel-to-q 500 700 900 ps t pd tempco differential propagation delay temperature coefficient 90 fs/ o c note 9 100 ps t s set-up time en-to-clk0 en-to-clk1 note 9 0 ps note 9 500 ps t h hold time clk0-to-en clk1-to-en note 9 600 ps output-to-output skew note 10 25 ps note 11 200 ps t skew part-to-part skew clk0 part-to-part skew clk1 note 11 250 ps cycle-to-cycle jitter note 12 1 ps rms random jitter (rj) note 13 1 ps rms total jitter (tj) note 14 10 ps pp t jitter adjacent channel crosstalk-induced jitter note 15 0.7 ps rms t r, t f output rise/fall time (20% to 80%) at full output swing. 80 150 250 ps notes: 8. high-frequency ac-parameters are guar anteed by design and characterization. 9. set-up and hold times apply to synchronous applications that in tend to enable/disable before the next clock cycle. for async hronous applications, set-up and hold do not apply. 10. output-to-output skew is measured between two di fferent outputs under ident ical input transitions. 11. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs 12. cycle-to-cycle jitter definition: the va riation of periods between adjacent cycles, t n ? t n-1 where t is the time between rising edges of the output signal. 13. random jitter is measured with a k 28.7 character pattern, measured at micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 8 typical operating characteristics v cc = 2.5v, gnd = 0, v in = 400mv, r l = 100 ? across the output pair; t a = 25c, unless ot herwise stated. functional characteristics v cc = 2.5v, gnd = 0, v in = 400mv, r l = 100 ? across the output pair; t a = 25c, unless ot herwise stated.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 9 single-ended and di fferential swings figure 1a. single-ended voltage swing clk0 figure 1b. differential voltage swing clk0 timing diagrams differential in-to-differential out clk_sel-to-differential out set-up and hold time en-to-differential in /clk clk /q q t pd clk_sel /q q t pd t pd ~ ~ ~ ~ ~ ~ v cc /2 v cc /2 /clk clk /q q t s en t h v cc /2 v cc /2
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 10 input and output stages figure 2a. clk1 differential input structure figure 2b. clk0 differential input structure clk0 input interface applications figure 3a. lvpecl interface (dc-coupled) figure 3b. lvpecl interface (ac-coupled) option: may connect vt to v cc figure 3c. cml interface (dc-coupled) figure 3d. cml interface (ac-coupled) figure 3e. lvds interface
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 11 clk1 input interface applications figure 4a. cml, lvds interface (dc-coupled) figure 4b. cml interface (dc-coupled) figure 4c. pecl interface (dc-coupled) figure 4d. pecl interface (ac-coupled) figure 4e. pecl interface (single-ended) (see single-ended ttl/cmos recommended resistor table for recommended resistor value r) figure 4f. ttl/cmos interface (single-ended)
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 12 single-ended ttl/cmos recommended resistor value the sy89113u can be driven by a ttl/cmos input signal. see figure 4f. the resistor r, in table 1, below is calculated according to the following equation: r = 1.594 1 5.057 v cc 2 v cc + v ih + v il ? 1 ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? the equation above is used to determine the optimum value of r for best duty cycle. recommended r ( ? ) 1.8v cmos 261 2.5v cmos 732 3.3v cmos 1470 table 1. single-ended ttl/cmos recommended resistors lvds output interface applications lvds specifies a small swing of 325mv typical, on a nominal 1.2v common mode above ground. the common mode voltage has tight limits to permit large variations in ground between an lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 5a. lvds differential measurement figure 5b. lvds common mode measurement related product and su pport documentation part number function data sheet link SY89112U 2.5/3.3v low jitter, low skew 1:12 lvpecl fanout buffer with 2:1 input mux and internal termination http://www.micrel.com/product-info/products/SY89112U.shtml hbw solutions new products and applications www.micrel.com/product-info/ products/solutions.shtml mlf tm application note www.amkor.com/p roducts/notes_papers/mlfappnote.pdf
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 13 package information 44-pin mlf? (mlf-44) 44-pin mlf? (mlf-44) package notes: 1. package meets level 2 moisture sensitivity classification, and is shipped in dry pack form. 2. exposed pads must be soldered to a ground for proper thermal management.
micrel, inc. sy89113u march 2005 m9999-032905 hbwhelp@micrel.com or (408) 955-1690 14 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel fo r its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended fo r surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support app liances, devices or sy stems is a purchaser ?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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